The present disclosure relates to semiconductor memories, and more particularly to static random-access memories (SRAMs).
Memory cells are required to exhibit two conflicting types of characteristics: one is excellent data retention characteristics, which ensure that stored data will not be easily lost, and the other is excellent write characteristics, which enable data to be easily rewritten. Variation in device characteristics is a major factor in these characteristics. It is known that a reduction in cell area results in a greater variation in device characteristics. Thus, it is becoming more difficult to keep the characteristics of the memory cell while reducing the cell area.
In general, when data in an SRAM cell is rewritten, an electrical charge is caused to flow from a latch in the cell to a bit line to invert the data in the latch. However, a current supplied from a power source to the latch interferes with this current flow. A large variation in characteristics of transistors included in the memory cell, and/or a low supply voltage, may create difficulties in rewriting data.
Japanese Patent Publication No. H09-045081 (Patent Document 1) describes an example of a memory having a switch between a power source and a memory cell. This memory improves write characteristics by interrupting power supply to memory cells on a row-by-row basis during a write operation.